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Alliance Memory DDR2 SDRAM

Alliance Memory DDR2 SDRAM is designed to comply with DDR2 SDRAM key features. Features such as posted CAS# with additive latency, Write latency=Read latency -1, and On-Die Termination (ODT). All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and DQS#) in a source synchronous fashion. The address bus is used to convey row, column, and bank address information in RAS #, CAS# multiplexing style.

Accesses begin with the registration of the Bank Activate command, and then it is followed by a Read or Write command. Read and write accesses to the DDR2 SDRAM are 4 or 8-bit burst oriented. Accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Operating the eight memory banks in an interleaved fashion allows random access operation to occur at a higher rate. An auto precharge function may be enabled to provide a self-timed row precharge. The self-timed row precharge is initiated at the end of the burst sequence. A sequential and gapless data rate is possible depending on burst length, CAS latency, and speed grade of the device.

Features

  • JEDEC Standard Compliant
  • JEDEC standard 1.8V I/O (SSTL_18-compatible)
  • Power supplies: VDD & VDDQ = +1.8V ± 0.1V
  • Commercial operating temperature range: 0°C~ 85°C
  • Industrial operating temperature range: -40°C~ 95°C
  • Fully synchronous operation
  • Fast clock rate of 400MHz
  • Differential Clock, CK & CK#
  • Bidirectional single/differential data strobe
  • 4-bit prefetch architecture
  • Internal pipeline architecture
  • Precharge & active power down
  • Programmable Mode & Extended Mode registers
  • Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, and 6
  • WRITE latency = READ latency - 1 tCK
  • Burst lengths: 4 or 8
  • Burst Type: Sequential / Interleave
  • DLL enable/disable
  • On-die termination (ODT)
  • RoHS compliant
  • Auto-refresh and self-refresh
  • 8192 refresh cycles / 64ms
  • Lead and Halogen-free package
Publicado: 2014-02-27 | Actualizado: 2022-03-11