The quad ADC cores use a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. Users can operate the AD6684 Receivers in DDC, NSR, and VDR modes via SPI-programmable profiles. Each pair of ADC data outputs connects to two DDCs using a crossbar mux. Each DDC consists of up to five cascaded signal processing stages, including a 48-bit frequency translator, NCO, and up to four half-band decimation filters. The ADC outputs connect to an NSR block. AD6684's integrated NSR circuitry delivers improved SNR performance in a smaller frequency band within the Nyquist bandwidth while maintaining a 9-bit output resolution.