Analog Devices Inc. AD9081 MxFE® Quad ADCs

Analog Devices Inc. AD9081 MxFE® Quad ADCs are highly integrated devices with four 16-bit, 12GSPS maximum sample rate, and an RF digital-to-analog converter (DAC) cores, and four 12-bit, 4GSPS rate, RF analog-to-digital converter (ADC) cores.

The ADI AD9081 MxFE Quad ADCs are intended for applications requiring both wideband ADCs and DACs to process signal(s) with wide instantaneous bandwidth. The AD9081 features eight transmit and eight receive lanes that support 24.75Gbps/lane JESD204C or 15.5Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier and a digital signal processing (DSP) capability targeted at either wideband or multiband direct to RF applications.

The AD9081 has two models available. The 4D4AC model supports the full instantaneous channel bandwidth. In contrast, the 4D4AB model supports a maximum fast bandwidth of 600MHz per channel by automatically configuring the DSP to limit the instantaneous bandwidth at startup.


  • Flexible, reconfigurable common platform design
    • 4 DACs and 4 ADCs (4D4A)
    • Supports single-, dual-, and quad-band
    • Datapaths and DSP blocks are fully bypassable
    • DAC to ADC sample rate ratios of 1, 2, 3, and 4
    • On-chip PLL with multichip synchronization
      • External RFCLK input option for off-chip PLL
  • Maximum DAC sample rate up to 12GSPS
    • Maximum data rate up to 12GSPS using JESD204C
    • Useable analog bandwidth to 8GHz
  • Maximum ADC sample rate up to 4GSPS
    • Maximum data rate up to 4GSPS using JESD204C
    • 7.5GHz analog input full power bandwidth (−3dB)
  • ADC ac performance at 4GSPS
    • Full-scale input voltage: 1.4V p-p
    • Noise density: -151.5dBFS/Hz
    • HD2: -68dBFS at 2.7GHz (tone at -1dBFS)
    • HD3: -75dBFS at 2.7GHz (tone at -1dBFS)
    • Worst other (excluding HD2 and HD3): -82dBFS at 2.7GHz
  • DAC ac performance at 12GSPS
    • Full-scale output current range of 7mA to 40mA
    • 2-tone IMD3 (-7dBFS per tone) of -78.9dBc
    • NSD, single-tone at 3.7GHz of -155.1dBc/Hz
    • SFDR, single-tone at 3.7GHz of -70dBc
    • SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75Gbps
      • 8 lanes JESD204B/C Tx (JTx) and 8 lanes JESD204B/C Rx (JRx)
      • Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
  • Versatile digital features
    • Selectable interpolation and decimation filters
    • Configurable or By-passable DDCs and DUCs
      • 8 fine complex DUCs and 4 coarse complex DUCs
      • 8 fine complex DDCs and 4 coarse complex DDCs
      • 48-bit NCO per DUC or DDC
  • Programmable 192-tap PFIR filter for receive equalization
    • Supports 4 different profile settings loaded via GPIO
  • Programmable delay per datapath
  • Receive AGC support
    • Fast detect with low latency for fast AGC control
    • Signal monitor for slow AGC control
    • Dedicated AGC support pins
  • Transmit DPD support
    • Fine DUC channel gain control and delay adjust
    • Coarse DDC delay adjust for DPD observation path
  • Auxiliary features
    • Fast frequency hopping
    • Direct digital synthesis (DDS)
    • Low latency digital loopback mode (Rx datapath data can be routed to the Tx datapaths)
    • ADC clock driver with selectable divide ratios
    • Power amplifier downstream protection circuitry
    • On-chip temperature monitoring unit
    • Flexible GPIO pins
    • TDD power savings option and sharing ADCs
  • 15mm x 15mm, 324-ball BGA with 0.8mm pitch


  • Wireless communications infrastructure
  • Microwave point-to-point, E-band and 5G mmWave
  • Broadband communications systems
  • DOCSIS 3.1 and 4.0 CMTS
  • Phased array radar and electronic warfare
  • Electronic test and measurement systems


Block Diagram - Analog Devices Inc. AD9081 MxFE® Quad ADCs
Publicado: 2021-03-08 | Actualizado: 2022-03-11